ETHERNET SMART BRIDGE
Alberto Carboni, Alessio CiarciĆ , Jacopo Grecuccio, Lorenzo Zaia
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10 #include "stm32f4xx_hal.h"
11 #include "stm32f4xx_hal_sram.h"
12 #include "stm32f4xx.h"
15 #define FPGA_IPM_UINT8 uint8_t
16 #define FPGA_IPM_UINT16 uint16_t
17 #define FPGA_IPM_BOOLEAN int
18 #define FPGA_IPM_SEM FPGA_IPM_BOOLEAN
21 #define FPGA_IPM_CORE FPGA_IPM_UINT8
22 #define FPGA_IPM_ADDRESS FPGA_IPM_UINT8
23 #define FPGA_IPM_DATA FPGA_IPM_UINT16
24 #define FPGA_IPM_OPCODE FPGA_IPM_UINT8
27 #define FPGA_IPM_CORE_MASK 0b1111111u
28 #define FPGA_IPM_ADDRESS_MASK 0b111111u
29 #define FPGA_IPM_OPCODE_MASK 0b111111u
32 #define FPGA_IPM_OPCODE_OFFSET 10
35 #define FPGA_IPM_BEGIN_TRANSACTION 0b0000000010000000u
36 #define FPGA_IPM_ACK 0b0000000100000000u
37 #define FPGA_IPM_INTERRUPT_MODE 0b0000001000000000u
38 #define FPGA_IPM_SRAM_BASE_ADDR 0x60000000U
54 FPGA_IPM_BOOLEAN
FPGA_IPM_open(FPGA_IPM_CORE coreID, FPGA_IPM_OPCODE opcode, FPGA_IPM_BOOLEAN interruptMode, FPGA_IPM_BOOLEAN ack);
62 FPGA_IPM_BOOLEAN
FPGA_IPM_read(FPGA_IPM_CORE coreID, FPGA_IPM_ADDRESS address, FPGA_IPM_DATA *dataPtr);
70 FPGA_IPM_BOOLEAN
FPGA_IPM_write(FPGA_IPM_CORE coreID, FPGA_IPM_ADDRESS address, FPGA_IPM_DATA *dataPtr);
FPGA_IPM_BOOLEAN FPGA_IPM_open(FPGA_IPM_CORE coreID, FPGA_IPM_OPCODE opcode, FPGA_IPM_BOOLEAN interruptMode, FPGA_IPM_BOOLEAN ack)
Opens a transaction with a given IP core.
Definition: Fpgaipm.c:250
FPGA_IPM_BOOLEAN FPGA_IPM_write(FPGA_IPM_CORE coreID, FPGA_IPM_ADDRESS address, FPGA_IPM_DATA *dataPtr)
Writes a 16-bit word in the buffer.
Definition: Fpgaipm.c:275
FPGA_IPM_BOOLEAN FPGA_IPM_close(FPGA_IPM_CORE coreID)
Closes a transaction with a given IP core.
Definition: Fpgaipm.c:286
FPGA_IPM_BOOLEAN FPGA_IPM_init(void)
Initialise CPU-FPGA communication environment.
Definition: Fpgaipm.c:29
FPGA_IPM_BOOLEAN FPGA_IPM_read(FPGA_IPM_CORE coreID, FPGA_IPM_ADDRESS address, FPGA_IPM_DATA *dataPtr)
Reads a 16-bit word from the buffer.
Definition: Fpgaipm.c:264