ETHERNET SMART BRIDGE
Alberto Carboni, Alessio CiarciĆ , Jacopo Grecuccio, Lorenzo Zaia
Functions
Fpgaipm.c File Reference

Low-level APIs for CPU-FPGA communication in an IP-Manager-based environment. More...

#include "Fpgaipm.h"
#include "stm32f4xx.h"
#include "stm32f4xx_hal.h"
#include "stm32f4xx_hal_sram.h"
#include "stm32f4xx_exti.h"
#include "stm32f4xx_syscfg.h"
#include "misc.h"

Functions

FPGA_IPM_BOOLEAN FPGA_IPM_init ()
 Initialise CPU-FPGA communication environment. More...
 
FPGA_IPM_BOOLEAN FPGA_IPM_open (FPGA_IPM_CORE coreID, FPGA_IPM_OPCODE opcode, FPGA_IPM_BOOLEAN interruptMode, FPGA_IPM_BOOLEAN ack)
 Opens a transaction with a given IP core. More...
 
FPGA_IPM_BOOLEAN FPGA_IPM_read (FPGA_IPM_CORE coreID, FPGA_IPM_ADDRESS address, FPGA_IPM_DATA *dataPtr)
 Reads a 16-bit word from the buffer. More...
 
FPGA_IPM_BOOLEAN FPGA_IPM_write (FPGA_IPM_CORE coreID, FPGA_IPM_ADDRESS address, FPGA_IPM_DATA *dataPtr)
 Writes a 16-bit word in the buffer. More...
 
FPGA_IPM_BOOLEAN FPGA_IPM_close (FPGA_IPM_CORE coreID)
 Closes a transaction with a given IP core. More...
 
void EXTI9_5_IRQHandler (void)
 

Detailed Description

Low-level APIs for CPU-FPGA communication in an IP-Manager-based environment.

Author
Alessandro Monaco, Simone Machetti, Gianluca Roascio, Flavio Ponzina

Function Documentation

◆ FPGA_IPM_close()

FPGA_IPM_BOOLEAN FPGA_IPM_close ( FPGA_IPM_CORE  coreID)

Closes a transaction with a given IP core.

Parameters
coreIDunique identifier/address of the core
Returns
true (1) on success

◆ FPGA_IPM_init()

FPGA_IPM_BOOLEAN FPGA_IPM_init ( void  )

Initialise CPU-FPGA communication environment.

Returns
true (1) on success

Perform the FPGA CS1 memory initialization sequence

Perform the FPGA CS2 memory initialization sequence

FMC GPIO Configuration PF0 ---—> FMC_A0 PF1 ---—> FMC_A1 PF2 ---—> FMC_A2 PF3 ---—> FMC_A3 PF4 ---—> FMC_A4 PF5 ---—> FMC_A5 PE7 ---—> FMC_D4 PE8 ---—> FMC_D5 PE9 ---—> FMC_D6 PE10 ---—> FMC_D7 PE11 ---—> FMC_D8 PE12 ---—> FMC_D9 PE13 ---—> FMC_D10 PE14 ---—> FMC_D11 PE15 ---—> FMC_D12 PD8 ---—> FMC_D13 PD9 ---—> FMC_D14 PD10 ---—> FMC_D15 PD14 ---—> FMC_D0 PD15 ---—> FMC_D1 PD0 ---—> FMC_D2 PD1 ---—> FMC_D3 PD4 ---—> FMC_NOE PD5 ---—> FMC_NWE PD7 ---—> FMC_NE1 PG9 ---—> FMC_NE2

◆ FPGA_IPM_open()

FPGA_IPM_BOOLEAN FPGA_IPM_open ( FPGA_IPM_CORE  coreID,
FPGA_IPM_OPCODE  opcode,
FPGA_IPM_BOOLEAN  interruptMode,
FPGA_IPM_BOOLEAN  ack 
)

Opens a transaction with a given IP core.

Parameters
coreIDunique identifier/address of the core
opcodeoperative code to be sent to the core
interruptModeto be set at 1 if the transaction is in interrupt mode, at 0 if it is in polling mode
ackto be set at 1 if the transaction is an acknowledge transaction, at 0 if it is not
Returns
true (1) on success

◆ FPGA_IPM_read()

FPGA_IPM_BOOLEAN FPGA_IPM_read ( FPGA_IPM_CORE  coreID,
FPGA_IPM_ADDRESS  address,
FPGA_IPM_DATA *  dataPtr 
)

Reads a 16-bit word from the buffer.

Parameters
coreIDunique identifier/address of the core
addressmemory offset within the buffer (from 0x01 (1) to 0x3F (63))
dataPtrpointer to be filled with the data read
Returns
true (1) on success

◆ FPGA_IPM_write()

FPGA_IPM_BOOLEAN FPGA_IPM_write ( FPGA_IPM_CORE  coreID,
FPGA_IPM_ADDRESS  address,
FPGA_IPM_DATA *  dataPtr 
)

Writes a 16-bit word in the buffer.

Parameters
coreIDunique identifier/address of the core
addressmemory offset within the buffer (from 0x01 (1) to 0x3F (63))
dataPtrpointer to the data to be written
Returns
true (1) on success